S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 322

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.4
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
322
Address: 0x0027
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
0
0
7
Debug Match Flag Register (DBGMFR)
Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
= Unimplemented or Reserved
0
0
6
Table 8-27. State3 — Sequencer Next State Selection
Figure 8-12. Debug Match Flag Register (DBGMFR)
Match1 triggers to Final State....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
MC9S12XE-Family Reference Manual , Rev. 1.23
Match0 triggers to State1....... Other matches have no effect
Match1 triggers to State1....... Other matches have no effect
Match0 triggers to State2....... Other matches have no effect
Match1 triggers to State2....... Other matches have no effect
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Table 8-42
5
0
0
Any match triggers to Final State
dictate that in the case of simultaneous matches, the match
Any match triggers to state1
Any match triggers to state2
0
0
4
Description
MC3
0
3
MC2
2
0
Freescale Semiconductor
MC1
0
1
MC0
0
0