MCIMX355AJQ5CR2 Freescale Semiconductor, MCIMX355AJQ5CR2 Datasheet - Page 114

• Manufacturer Part Number: MCIMX355AJQ5CR2
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5CR2

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.22
This section describes electrical characteristics of the SSI.
114
(Output)
STCLK
(Input)
SRCK
SSI Electrical Specifications
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•
•
•
All of the timing for the SSI is given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timing is on AUDMUX signals when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the transmit and receive sections of the SSI,
respectively.
For internal frame sync operations using the external clock, the FS
timing will be the same as that of Tx Data (for example, during AC97
mode of operation).
i.MX35 Applications Processors for Automotive Products, Rev. 9
Figure 92. STCLK Timing
Figure 91. SRCK Timing
stclkpl
srckpl
V
V
M
M
NOTE
stclkp
srckp
stclkph
srckph
V
V
M
M
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