MCIMX355AJQ5CR2 Freescale Semiconductor, MCIMX355AJQ5CR2 Datasheet - Page 8

• Manufacturer Part Number: MCIMX355AJQ5CR2
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5CR2

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8
Mnemonic
AUDMUX
CSPI(2)
CAN(2)
EPIT(2)
Block
CCM
ECT
EMI
ATA
cross trigger
memory
interface
periodic
interrupt timer
ATA module
Digital audio
mux
CAN module
Clock control
module
Configurable
serial
peripheral
interface
Embedded
External
Enhanced
Block Name
i.MX35 Applications Processors for Automotive Products, Rev. 9
SDMA
ARM
ARM
ARM
SDMA,
ARM
SDMA,
ARM
SDMA
ARM
Domain
Table 4. Digital and Analog Modules (continued)
1
Connectivity
peripherals
Multimedia
peripherals
Connectivity
peripherals
Clocks
Connectivity
peripherals
Debug
External
memory
interface
Timer
peripherals
Subsystem
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.
The CAN protocol is primarily designed to be used as a vehicle
serial data bus running at 1 Mbps.
This block generates all clocks for the peripherals in the SDMA
platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.
This module is a serial interface equipped with data FIFOs; each
master/slave-configurable SPI module is capable of interfacing to
both serial port interface master and slave devices. The CSPI ready
(SPI_RDY) and slave select (SS) control signals enable fast data
communication with fewer software interrupts.
ECT (embedded cross trigger) is an IP for real-time debug
purposes. It is a programmable matrix allowing several subsystems
to interact with each other. ECT receives signals required for
debugging purposes (from cores, peripherals, buses, external
inputs, and so on) and propagates them (propagation programmed
through software) to the different debug resources available within
the SoC.
The EMI module provides access to external memory for the ARM
and other masters. It is composed of the following main
submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.
Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.
Brief Description
Freescale Semiconductor