MCIMX355AJQ5CR2 Freescale Semiconductor, MCIMX355AJQ5CR2 Datasheet - Page 53

• Manufacturer Part Number: MCIMX355AJQ5CR2
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5CR2

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
DDR17 DQ and DQM setup time to DQS (single-ended strobe)
DDR18 DQ and DQM hold time to DQS (single-ended strobe)
DDR19 Write cycle DQS falling edge to SDCLK output setup time.
DDR20 Write cycle DQS falling edge to SDCLK output hold time.
DDR21 DQS latching rising transitions to associated clock edges
DDR22 DQS high level width
DDR23 DQS low level width
ID
DQM (output)
DQS (output)
DQ (output)
SDCLK_B
These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of
1 V/ns. For different values use the derating table.
SDCLK
i.MX35 Applications Processors for Automotive Products, Rev. 9
Figure 32. DDR2 SDRAM Write Cycle Timing Diagram
PARAMETER
Figure 33. DDR2 SDRAM Write Cycle Parameters
DDR21
DDR17
DDR17
Data
DM
DDR18
DDR18
Data
DM
NOTE
DDR17
DDR17
Data
DM
DDR22
t
t
Symbol
DH1(base)
DS1(base)
Data
DM
t
t
t
t
DQSS
DQSH
t
DQSL
DSS
DSH
DDR23
DDR18
DDR18
Data
DM
0.025
0.025
–0.25
Data
0.35
0.35
Min
DM
0.2
0.2
DDR19
DDR2-400
Data
DM
Max
0.25
—
—
—
—
—
—
Data
DM
DDR20
Unit
tCK
tCK
tCK
tCK
tCK
ns
ns
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