MCIMX355AJQ5CR2 Freescale Semiconductor, MCIMX355AJQ5CR2 Datasheet - Page 63

• Manufacturer Part Number: MCIMX355AJQ5CR2
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5CR2

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.8.3
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
1
Figure 41
4.9.8.4
The MII asynchronous timing signals are FEC_CRS and FEC_COL.
inputs signal timing.
1
Freescale Semiconductor
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
Num
Num
M5
M6
M7
M8
M9
1
FEC_TXD[3:0] (outputs)
FEC_TX_CLK pulse width high
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
FEC_TX_CLK pulse width low
shows the MII transmit signal timings listed in
FEC_TX_CLK (input)
MII Transmit Signal Timing
MII Asynchronous Inputs Signal Timing
FEC_TX_EN
FEC_TX_ER
FEC_CRS to FEC_COL minimum pulse width
i.MX35 Applications Processors for Automotive Products, Rev. 9
Characteristic
Characteristic
Figure 41. MII Transmit Signal Timing Diagram
Table 47. MII Asynch Inputs Signal Timing
Table 46. MII Transmit Signal Timing
1
M5
Table 46
M6
M7
Table
lists MII transmit channel timings.
46.
Min.
35%
35%
Min.
1.5
—
5
Table 47
M8
Max.
Max.
65%
65%
20
—
—
lists MII asynchronous
FEC_TX_CLK period
FEC_TX_CLK period
FEC_TX_CLK period
Unit
Unit
ns
ns
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