MCIMX355AJQ5CR2 Freescale Semiconductor, MCIMX355AJQ5CR2 Datasheet - Page 55

• Manufacturer Part Number: MCIMX355AJQ5CR2
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5CR2

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
0.45 × tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.
1
Freescale Semiconductor
The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =
SD17
SD18
SD19
SD20
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
DDR24
DDR25
DDR26
ID
Write cycle DQS falling edge to SDCLK output delay time.
Write cycle DQS falling edge to SDCLK output hold time.
DQ and DQM setup time to DQS
DQ and DQM hold time to DQS
DQM (output)
DQS (output)
DQ (output)
SDCLK
SDCLK
DQS – DQ Skew (defines the Data valid window in
read cycles related to DQS).
DQS DQ in HOLD time from DQS
DQS output access time from SDCLK posedge
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value. DDR SDRAM CLK parameters are measured at the
crossing point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
Table 41. Mobile DDR SDRAM Write Cycle Timing Parameters
Figure 35. Mobile DDR SDRAM Write Cycle Timing Diagram
i.MX35 Applications Processors for Automotive Products, Rev. 9
Table 40. DDR2 SDRAM Read Cycle Parameter Table
PARAMETER
SD17
SD17
Parameter
Data
DM
1
SD18
SD18
Data
DM
NOTE
Data
SD17
DM
SD17
Symbol
Data
DM
t
t
DQSCK
DQSQ
t
QH
SD18
SD18
Data
DM
Symbol
2.925
–0.5
Data
tDSH
Min
tDSS
DM
tDS
tDH
—
SD19
DDR2-400
1
Data
DM
Min.
0.95
0.95
1.8
1.8
SD20
Max
0.35
0.5
—
Data
DM
Max.
—
—
—
—
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
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