HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 276

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 User Break Controller
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ
0
1
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 0: ETBE
0
1
8.2.10
When the execution-times break condition of channel B is enabled, this register specifies the
number of execution times to make the break. The maximum number is 2
reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A
break is issued when the break condition is satisfied after the BETR becomes H'0001. Bits 15 to
12 are always read as 0 and 0 should always be written in these bits.
Rev.6.00 Mar. 27, 2009 Page 218 of 1036
REJ09B0254-0600
Initial value:
R/W:
Bit:
Execution Times Break Register (BETR)
15
—
R
0
Description
Channels A and B are compared under the independent condition (Initial value)
Channels A and B are compared under the sequential condition
Description
The execution-times break condition is disabled on channel B
The execution-times break condition is enabled on channel B
14
—
R
0
13
—
R
0
12
—
R
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
0
8
R/W
7
0
R/W
0
6
R/W
5
0
R/W
12
0
4
– 1 times. A power-on
R/W
3
0
R/W
(Initial value)
2
0
R/W
1
0
R/W
0
0