HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 369

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12.2.8
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000
by a power-on reset, but is not initialized by a manual reset or standby mode. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): The CMF status flag indicates that the values of RTCNT
and RTCOR match.
Bit 7: CMF
0
1
Note: * Contents do not change when 1 is written to CMF.
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request
caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS
refresh or auto-refresh.
Bit 6: CMIE
0
1
Initial value:
R/W:
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit:
Refresh Timer Control/Status Register (RTCSR)
15
—
R
0
14
—
R
0
Description
The values of RTCNT and RTCOR do not match.
Clear condition: When a refresh is performed After 0 has been written in
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh).
The values of RTCNT and RTCOR match.
Set condition: RTCNT = RTCOR*
Description
Disables an interrupt request caused by CMF
Enables an interrupt request caused by CMF
13
—
R
0
12
—
R
0
11
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
Rev.6.00 Mar. 27, 2009 Page 311 of 1036
CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
R/W
7
0
Section 12 Bus State Controller (BSC)
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0254-0600
R/W
2
0
(Initial value)
(Initial value)
R/W
1
0
R/W
0
0