HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 34

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

25.2 Register Descriptions ........................................................................................................ 767
25.3 Operation........................................................................................................................... 790
25.4 Clock and LCD Data Signal Examples ............................................................................. 809
25.5 Usage Notes ...................................................................................................................... 819
Section 26 Pin Function Controller (PFC)
26.1 Overview........................................................................................................................... 821
26.2 Register Configuration...................................................................................................... 826
26.3 Register Descriptions ........................................................................................................ 827
Rev.6.00 Mar. 27, 2009 Page xxxii of lvi
REJ09B0254-0600
25.2.1 LCDC Input Clock Register (LDICKR) .............................................................. 767
25.2.2 LCDC Module Type Register (LDMTR) ............................................................ 768
25.2.3 LCDC Data Format Register (LDDFR)............................................................... 771
25.2.4 LCDC Scan Mode Register (LDSMR) ................................................................ 773
25.2.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) .......... 774
25.2.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) .......... 775
25.2.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) .......... 776
25.2.8 LCDC Palette Control Register (LDPALCR)...................................................... 777
25.2.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ...................................... 778
25.2.10 LCDC Horizontal Character Number Register (LDHCNR) ................................ 779
25.2.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ........................................ 780
25.2.12 LCDC Vertical Display Line Number Register (LDVDLNR)............................. 781
25.2.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................. 782
25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR) ............................................ 783
25.2.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ...... 784
25.2.16 LCDC Interrupt Control Register (LDINTR) ...................................................... 784
25.2.17 LCDC Power Management Mode Register (LDPMMR)..................................... 786
25.2.18 LCDC Power-Supply Sequence Period Register (LDPSPR) ............................... 788
25.2.19 LCDC Control Register (LDCNTR).................................................................... 789
25.3.1 LCD Module Sizes which can be Displayed in this LCDC ................................. 790
25.3.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected
25.3.3 Color Palette Specification................................................................................... 797
25.3.4 Data Format ......................................................................................................... 799
25.3.5 Timing Controller Register .................................................................................. 802
25.3.6 Power Management Registers.............................................................................. 802
25.3.7 Operation for Hardware Rotation......................................................................... 807
26.3.1 Port A Control Register (PACR) ......................................................................... 827
26.3.2 Port B Control Register (PBCR).......................................................................... 828
26.3.3 Port C Control Register (PCCR).......................................................................... 829
26.3.4 Port D Control Register (PDCR) ......................................................................... 830
26.3.5 Port E Control Register (PECR) .......................................................................... 831
Memory (SDRAM).............................................................................................. 791
................................................................... 821