HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 99

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.6
SH7727 CPU
MOV.W
ADD
........
.DATA.W H'1234
Note: Immediate data is referenced by @(disp,PC).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches.
With a delayed branch instruction, the branch is made after execution of the instruction (called the
slot instruction) immediately following the delayed branch instruction. This minimizes disruption
of the pipeline when a branch is made.
With a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution for register updating, etc., excluding the branch operation, is
performed in delayed branch instruction → delay slot instruction order. For example, even though
the contents of the register holding the branch destination address are changed in the delay slot,
the branch destination address remains as the register contents prior to the change.
Table 2.7
SH7727 CPU
BRA
ADD
Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is
executed in 1 to 3 states, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in 2 to 3
states. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-accumulate
operation are each executed in 2 to 5 states.
T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a
conditional branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum.
TRGET
R1,R0
@(disp,PC),R1
R1,R0
Word Data Sign Extension
Delayed Branch Instructions
Description
ADD is executed before branch to
TRGET.
Description
Sign-extended to 32 bits, R1
becomes H'00001234, and is
then operated on by the ADD
instruction.
Rev.6.00 Mar. 27, 2009 Page 41 of 1036
Example of Other CPU
ADD.W R1,R0
BRA
Example of Other CPU
ADD.W
TRGET
#H'1234,R0
REJ09B0254-0600
Section 2 CPU