HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 288

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 User Break Controller
Break Condition Specified to a CPU Data Access Cycle
1. Register specifications
2. Register specifications
Rev.6.00 Mar. 27, 2009 Page 230 of 1036
REJ09B0254-0600
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, a user break occurs with ASID = H'80 during longword read to address
H'00123454, word read to address H'00123456, or byte read to address H'00123456. On
channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses
H'000ABC00 to H'000ABCFE.
BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000,
BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000,
BRCR = H'00300080
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, a user break occurs during word read to address H'01000000 on the memory
space. On channel B, a user break occurs when word H'4567 is written in address H'0001F000
Address:
Bus cycle: CPU/data access/read (operand size is not included in the condition)
Address:
Data:
Bus cycle: CPU/data access/write/word
Address:
Bus cycle: CPU/data access/read/word
No ASID check is included
Y Address: H'0001F000, Address mask: H'FFFF0000
Data:
Bus cycle: CPU/data access/write/word
No ASID check is included
Channel A
Channel B
Channel A
Channel B
H'00123456, Address mask: H'00000000, ASID: H'80
H'000ABCDE, Address mask: H'000000FF, ASID: H'70
H'0000A512, Data mask: H'00000000
H'01000000, Address mask: H'00000000
H'00004567, Data mask: H'00000000