UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 239

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(8) Oscillation stabilization time select register (OSTS)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be
checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Address: FFA4H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before
Figure 6-11. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
1
1
After reset: 05H
2. Do not change the value of the OSTS register during the X1 clock oscillation
3. The oscillation stabilization time counter counts up to the oscillation stabilization
4. The X1 clock oscillation stabilization wait time does not include the time until clock
X
: X1 clock oscillation frequency
Other than above
executing the STOP instruction.
stabilization time.
time set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
oscillation starts (“a” below).
OSTS1
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
6
0
0
1
1
0
0
by OSTS
X1 pin voltage
waveform
R/W
OSTS0
5
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
Setting prohibited
11
13
14
15
16
/f
/f
/f
/f
/f
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
204.8
819.2
1.64 ms
3.27 ms
6.55 ms
CHAPTER 6 CLOCK GENERATOR
f
X
μ
μ
OSTS2
= 10 MHz
s
s
2
OSTS1
102.4
409.6
819.2
1.64 ms
3.27 ms
1
f
X
μ
μ
μ
= 20 MHz
s
s
s
OSTS0
0
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