UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 532

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(2) Automatic transmit/receive data setting
Here is an example of the procedure for successively transmitting/receiving data as the master.
<1> Enable CSIA0 to operate by setting bit 7 (CSIAE0) of serial operation mode specification register 0
<2> Select a serial clock by using serial status register 0 (CSIS0).
<3> Set the division ratio of the serial clock by using division value selection register 0 (BRGCA0), and specify a
<4> Sequentially write data to be transmitted to the buffer RAM, starting from the least significant address
<5> Set “number of data items to be transmitted − 1” to automatic data transfer address point specification
<6> Set bits 6 (ATE0) and 4 (MASTER0) of CSIMA0 to select a master operation in the automatic
<7> Set bits 3 (TXEA0) and 2 (RXEA0) of CSIMA0 to 1 to enable transmission/reception.
<8> Set the transmission interval of data to the automatic data transfer interval specification register (ADTI0).
<9> Automatic transmit/receive processing is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is
Operations <1> to <9> execute the following operation.
• After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is
• The received data is written to the buffer RAM address indicated by ADTC0.
• ADTC0
• When automatic transmission/reception is terminated, an interrupt request (INTACSI) is generated and bit
• To continue transmitting the next data, set the new data to the buffer RAM, and set “number of data to be
(CSIMA0) to 1 (the buffer RAM can now be accessed).
communication rate.
FA00H, up to FA1FH. Data is transmitted from the lowest address, continuing on to higher addresses.
register 0 (ADTP0).
communication mode.
set to 1.
Caution Take the relationship with the other communicating party into consideration when setting
transferred to SIOA0, transmission is carried out (start of automatic transmission/reception).
transmission/reception continues until the ADTC0 incremental output matches the set value of automatic
data transfer address point specification register 0 (ADTP0) (end of automatic transmission/reception).
However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is cleared after a match between
ADTP0 and ADTC0, and then repeated transmission/reception is started.
0 (TSF0) of CSIS0 is cleared.
transmitted − 1” to ADTP0. After setting the number of data, set ATSTA0 to 1.
the port mode register and port register.
is
incremented
and
the
next
data
transmission/reception
CHAPTER 17 SERIAL INTERFACE CSIA0
is
carried
out.
Data
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