UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 958

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
UART0
Function
UART mode
TXS0: Transmit
shift register 0
ASIM0:
Asynchronous
serial interface
operation mode
register 0
ASIS0:
Asynchronous
serial interface
reception error
status register 0
BRGC0: Baud
rate generator
control register 0
Details of
Function
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped (e.g.,
in the STOP mode), each register stops operating, and holds the value immediately
before clock supply was stopped. The T
before clock supply was stopped and outputs it. However, the operation is not
guaranteed after clock supply is resumed. Therefore, reset the circuit so that
POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to
start communication.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of
base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within
two clocks of base clock, the transmission circuit or reception circuit may not be
initialized.
Set transmit data to TXS0 at least one base clock (f
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the
transmission, clear TXE0 to 0, and then clear POWER0 to 0.
To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the
reception, clear RXE0 to 0, and then clear POWER0 to 0.
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin.
If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is
started.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of
base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within
two clocks of base clock, the transmission circuit or reception circuit may not be
initialized.
Set transmit data to TXS0 at least one base clock (f
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed
with “number of stop bits = 1”, and therefore, is not affected by the set value of the
SL0 bit.
Be sure to set bit 0 to 1.
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0)
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer register
0 (RXB0) but discarded.
If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0
when the peripheral hardware clock (f
CAUTIONS FOR WAIT.
Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting
the MDL04 to MDL00 bits.
Make sure that bit 7 (POWER0) of the ASIM0 register = 0 when rewriting the TPS01
and TPS00 bits.
The baud rate value is the output clock of the 5-bit counter divided by 2.
PRS
Cautions
X
) is stopped. For details, see CHAPTER 36
D0 pin also holds the value immediately
APPENDIX D LIST OF CAUTIONS
XCLK0
XCLK0
XCLK0
XCLK0
) after setting TXE0 = 1.
) after setting TXE0 = 1.
) set by BRGC0. To
) set by BRGC0. To
p. 432
p. 432
p. 432
pp. 432,
435
p. 435
p. 437
p. 437
p. 437
p. 437
p. 437
p. 437
p. 437
p. 437
p. 438
p. 438
p. 438
p. 438
p. 440
p. 440
p. 440
Page
(15/30)
958