UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 968

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Standby
function
Reset
function
Power-on-
clear circuit
Function
OSTS:
Oscillation
stabilization time
select register
STOP mode
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
Details of
Function
−
−
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
Even if “internal low-speed oscillator can be stopped by software” is selected by the
option byte, the internal low-speed oscillation clock continues in the STOP mode in
the status before the STOP mode is set. To stop the internal low-speed oscillator’s
oscillation in the STOP mode, stop it by software and then execute the STOP
instruction.
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), switch the CPU clock
to the internal highspeed oscillation clock before the execution of the STOP
instruction using the following procedure.
<1> Set RSTOP to 0 (starting oscillation of the internal high-speed oscillator)
<2> Set MCM0 to 0 (switching the CPU from X1 oscillation to internal high-speed
oscillation)
RSTS is 1 (checking internal high-speed oscillation operation)
STOP instruction
Before changing the CPU clock from the internal high-speed oscillation clock to the
high-speed system clock (X1 oscillation) after the STOP mode is released, check the
oscillation stabilization time with the oscillation stabilization time counter status
register (OSTC).
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12
speed oscillation clock is selected as the CPU clock, or for the duration of 160
external clocks when the high-speed system clock (external clock input) is selected as
the CPU clock.
Execute the STOP instruction after having confirmed that the internal high-speed
oscillator is operating stably (RSTS = 1).
For an external reset, input a low level for 10
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock input
and external subsystem clock input become invalid.
When the STOP mode is released by a reset, the STOP mode contents are held
during reset input. However, the port pins become high-impedance, except for P130,
which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag register
(RESF) is cleared to 00H.
Set the low-voltage detector by software after the reset status is released
(see CHAPTER 25 LOW-VOLTAGE DETECTOR).
<3> Check that MCS is 0 (checking the CPU clock)
μ
s after the STOP mode is released when the internal high-
Cautions
μ
s or more to the RESET pin.
APPENDIX D LIST OF CAUTIONS
<5> Execute the
<4> Check that
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