UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 530

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
17.4.3 3-wire serial I/O mode with automatic transmit/receive function
operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number
of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and
stored in RAM.
generated by hardware are supported. Therefore, connection to peripheral ICs such as OSD (On Screen Display) ICs and
LCD controller/drivers can be easily realized.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial
In addition, to transmit/receive data continuously when used as the master, handshake signals (STB0 and BUSY0)
(1) Registers used
• Serial operation mode specification register 0 (CSIMA0)
• Serial status register 0 (CSIS0)
• Serial trigger register 0 (CSIT0)
• Divisor selection register 0 (BRGCA0)
• Automatic data transfer address point specification register 0 (ADTP0)
• Automatic data transfer interval specification register 0 (ADTI0)
• Port mode register 14 (PM14)
• Port register 14 (P14)
The relationship between the register settings and pins is shown below.
Caution A wait state may be generated when data is written to the buffer RAM.
CHAPTER 36 CAUTIONS FOR WAIT.
CHAPTER 17 SERIAL INTERFACE CSIA0
For details, see
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