UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 299

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2
7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input
mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the timer/event counter,
TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting operation, TM0n is cleared
to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected, TM0n overflows and continues
counting.
start of the operation.
(1) Operation in clear & start mode entered by TI00n pin valid edge input
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear & start
The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after the
CR00n and CR01n are used as compare registers and capture registers.
(a) When CR00n and CR01n are used as compare registers
(b) When CR00n and CR01n are used as capture registers
Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
(CR00n: compare register, CR01n: compare register)
Remark n = 0:
Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and
CR01n.
The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is
input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin).
When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the INTTM01n
signal is generated. As soon as the count value has been captured, the counter is cleared to 0000H.
Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
Count clock
TI00n pin
PRM0n1 and PRM0n0 = 11, TM0n may be cleared.
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
TMC0n3, TMC0n2
Operable bits
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
78K0/KD2 products
(CR00n: Compare Register, CR01n: Compare Register)
detection
Edge
Compare register
Timer counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Match signal
(CR01n)
(TM0n)
Compare register
Clear
(CR00n)
Match signal
controller
Output
TO0n output
Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
TO0n pin
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