UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 22

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20
(2) Internal units
(a) CPU
(b) Bus control unit (BCU)
(c) ROM
(d) RAM
(e) Interrupt controller (INTC)
(f) Clock generator (CG)
(g) Timer/counter
(h) Watchdog timer (WDT)
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits), help accelerate complex processing.
The BCU controls the internal bus.
This is flash memory that is mapped from address 00000000H.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles. The
internal ROM capacity and area differ as follows depending on the product.
Remark
This is a 6 KB internal RAM that is mapped to the addresses xnFFD800H to xnFFEFFFH.
During instruction fetch or data access, data can be accessed from the CPU in 1-clock cycles.
Remark
This controller handles hardware interrupt requests (INTP0 to INTP6) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple-interrupt servicing control can be performed.
The clock generator includes two basic operation modes: PLL mode (fixed to multiplication by eight) and
clock-through mode. It generates four types of clocks (f
the operating clock for the CPU (f
This unit incorporates one 16-bit interval timer M (TMM) channel, two 16-bit timer/event counter Q (TMQ)
channels, and four 16-bit timer/event counter P (TMP) channels, and can measure pulse interval widths or
frequency, enable an inverter function for motor control, and output a programmable pulse.
A watchdog timer is equipped to detect program loops, system abnormalities, etc.
It generates a non-maskable interrupt request signal (INTWDT) or internal reset signal (WDTRES) after an
overflow occurs.
μ
μ
PD70F3713
PD70F3714
n = xx11B
n = xx11B
Part Number
CHAPTER 1 INTRODUCTION
CPU
User’s Manual U17716EJ2V0UD
).
64 KB (flash memory)
128 KB (flash memory)
Internal ROM Capacity
XX
, f
XX
/2, f
XX
/4, f
XX
xn000000H to xn00FFFFH
xn000000H to xn01FFFFH
/8), and supplies one of them as
Internal ROM Area