UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 49

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.5
generation when operand data in the data space is accessed. The ±32 KB area of addresses stored in this pointer
can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that
can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation
when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and
the program size can be reduced.
The architecture of the V850ES/IE2 requires that a register that serves as a pointer be secured for address
(1) Program space
(2) Data space
Caution When a branch instruction is positioned at the upper limit of the internal RAM area, a
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access addresses 3FFD800H to 3FFEFFFH (6 KB).
With the V850ES/IE2 it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address
space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated
as an address.
Recommended use of address space
prefetch operation (invalid fetch) that will be located in the on-chip peripheral I/O area is not
generated.
CHAPTER 3 CPU FUNCTION
User’s Manual U17716EJ2V0UD
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