UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 517

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIB0 pin capture
INTCB0R signal
(2) Operation timing
CB0TSF bit
SCKB0 pin
SOB0 pin
SIB0 pin
(1) Write 00H to the CB0CTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CB0CTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CB0CTL0 register, and select the transmission/reception mode and MSB first at the
(4) The CB0STR.CB0TSF bit is set to 1 by writing the transmit data to the CB0TX register, and
(5) When transmission/reception is started, output the serial clock to the SCKB0 pin, output the transmit
(6) When transmission/reception of the transfer data length set with the CB0CTL2 register is completed,
(7) Read the CB0RX register.
(8) To continue transmission/reception, write the transmit data to the CB0TX register again.
(9) Read the CB0RX register.
(10) To end transmission/reception, write the CB0CTL0.CB0PWR bit = 0, the CB0CTL0.CB0TXE bit = 0,
timing
f
same time as enabling the operation of the communication clock (f
transmission/reception is started.
data to the SOB0 pin in synchronization with the serial clock, and capture the receive data of the SIB0
pin.
stop the serial clock output, transmit data output, and data capturing, generate the reception end
interrupt request signal (INTCB0R) at the last edge of the serial clock, and clear the CB0TSF bit to 0.
and the CB0CTL0.CB0RXE bit = 0.
XX
/2, and master mode.
(1)
(2)
(3)
(4)
(5)
Bit 7
Bit 7
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
User’s Manual U17716EJ2V0UD
Bit 1
Bit 1
(6)
(7)
Bit 0
Bit 0
(8)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
CCLK
Bit 4
Bit 4
).
Bit 3 Bit 2
Bit 3 Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
(9)
(10)
CCLK
) =
515