UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 431

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Analog input
Registers
Control registers
A/D converters 0 and 1 consist of the following hardware.
Remark
(1) Selector
(2) Sample & hold circuit
(3) Voltage comparator
(4) Array
The input circuit selects the analog input pin (ANIn0 to ANIn3) according to the mode set by the ADAnM0,
ADAnM1, ADAnM2, and ADAnS registers and sends the input to the sample & hold circuit (n = 0, 1).
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit,
and sends them to the voltage comparator. This circuit also holds the sampled analog input voltage during
A/D conversion.
This comparator compares the voltage generated from the voltage tap of the array with the analog input
voltage. If the analog input voltage is found to be greater than the reference voltage (1/2AV
the comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the
analog input voltage is less than the reference voltage (1/2AV
After that, bit 8 of the SAR is automatically set, and the next comparison is made. The voltage tap of the array
is selected by the value of bit 9, to which the result has been already set.
The voltage tap of the array and the analog input voltage are compared and bit 8 of the SAR is manipulated
according to the result of the comparison.
Comparison is continued like this to bit 0 of the SAR.
The array generates comparison voltage by the voltage input from an analog input pin (ANIn0 to ANIn3) (n = 0,
1).
Item
Bit 9 = 0: (1/4AV
Bit 9 = 1: (3/4AV
Analog input voltage ≥ Voltage tap of array: Bit 8 = 1
Analog input voltage ≤ Voltage tap of array: Bit 8 = 0
n = 0, 1
ANI00 to ANI03, ANI10 to ANI13 (two circuits, total of eight channels)
A/D converter n mode register 0 (ADAnM0)
Successive approximation register (SAR)
A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3)
A/Dn conversion result registers 0H to 3H (ADAnCR0H to ADAnCR3H)
A/D converter n mode register 1 (ADAnM1)
A/D converter n mode register 2 (ADAnM2)
A/D converter n channel specification register 0 (ADAnS)
REFn
REFn
Table 11-1. Configuration of A/D Converters 0 and 1
)
)
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
Configuration
REFn
), the MSB of the SAR is reset.
REFn
) as a result of
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