UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 391

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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9.4.3
• The interrupts to be culled are INTTQ1CC0 (crest interrupt) and INTTQ1OV (valley interrupt).
• The TQ1OPT1.TQ1ICE bit is used to enable output of the INTTQ1CC0 interrupt and the number of times the
• The TQ1OPT1.TQ1IOE bit is used to enable output of the INTTQ1OV interrupt and the number of times the
• The TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits are used to specify the number of times for which an interrupt,
• The TQ1RDE bit of TQ1OPT2 is used to specify whether transfer is to be culled or not.
• The TQ1OPT0.TQ1CMS bit is used to specify whether the registers with a transfer function are batch rewritten or
interrupt is to be culled.
interrupt is to be culled.
subject to counting of culling, is counted.
The interrupt is masked for the specified culling count and the masked interrupt occurs at the next occurrence
timing.
If it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after
culling. If it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the
TQ1CCR1 register has been written.
anytime rewritten.
The values of the registers are updated in synchronization with transferring when the TQ1CMS bit is 0. When the
TQ1CMS bit is 1, the values of the registers are immediately updated when a new value is written to the
registers.
Transfer is performed from the TQ1CCRm register to the CCRm buffer register in synchronization with interrupt
culling timing.
Cautions 1. When using the interrupt culling function in the batch rewrite mode (transfer mode),
Interrupt culling function
2. An interrupt is generated at the timing after culling.
execute the function in the intermittent batch rewrite mode (transfer culling mode).
CHAPTER 9 MOTOR CONTROL FUNCTION
User’s Manual U17716EJ2V0UD
389

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