UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 463

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.7 Operation in External Trigger Mode
timing.
the P05/INTP5 pin. To set the external trigger mode, set the PMC04 bit of port mode control register 0 (PMC0) to 1
and the ADA0M2.ADA0TMD1 bit to 0 with A/D converter 0. With A/D converter 1, set the PMC05 bit of port mode
control register 0 (PMC0) to 1 and the ADA1M2.ADA1TMD1 bit to 0.
rising and falling edges can be specified by setting the ADAnM0.ADAnETS1 and ADAnM0.ADAnETS0 bits.
the ADTRGn pin, starts A/D conversion.
and, at the same time, the A/Dn conversion end interrupt request signal (INTADn) is generated.
ADAnM0.ADAnMD1 and ADAnM0.ADAnMD0 bits.
converter is waiting for a trigger, the ADAnEF bit = 0 (conversion stopped).
beginning. If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the conversion is
stopped and the A/D converter waits for a trigger again.
In the external trigger mode, the analog input pins (ANIn0 to ANIn3) are A/D converted at the ADTRGn pin input
The ADTRG0 pin has an alternate function as the P04/INTP4 pin and the ADTRG1 pin has an alternate function as
For the valid edge of the external input signal in the external trigger mode, the rising edge, falling edge, or both
When the ADAnM0.ADAnCE bit is set (1), the A/D converter waits for a trigger and, when the trigger is input from
After the end of A/D conversion, the conversion result is stored in A/Dn conversion result register m (ADAnCRm)
After the end of A/D conversion, the A/D converter waits for a trigger regardless of the operation mode set by the
When conversion is started, the ADAnM0.ADAnEF bit is set to 1 (conversion in progress). However, while the A/D
If a valid trigger is input during A/D conversion, the conversion operation is stopped and started again from the
Remark
n = 0, 1
m = 0 to 3
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
461