PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 103

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

11.5.2
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I
bit is set, or the bus is idle and both the S and P bits are
clear.
In master mode the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 11-5:
Address
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
13h
93h
14h
94h
87h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear.
1997 Microchip Technology Inc.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
3: The SMP and CKE bits are implemented on the PIC16C66/67 only. All other PIC16C6X devices have these two bits unim-
MASTER MODE
Shaded cells are not used by SSP module in SPI mode.
plemented, read as '0'.
Name
INTCON
PIR1
PIE1
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPADD Synchronous Serial Port (I
SSPCON
SSPSTAT
TRISC
REGISTERS ASSOCIATED WITH I
2
PORTC Data Direction register
C bus may be taken when the P
PSPIE
PSPIF
SMP
WCOL
Bit 7
GIE
(3)
(1)
(1)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
SSPOV SSPEN
CKE
Bit 6
PEIE
(2)
(2)
(3)
RCIF
RCIE
Bit 5
T0IE
D/A
2
C mode) Address Register
INTE
Bit 4
TXIF
TXIE
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
2
RBIE
Bit 3
C OPERATION
S
11.5.3
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
Bit 2
T0IF
R/W
MULTI-MASTER MODE
INTF
Bit 1
UA
Bit 0
RBIF
BF
PIC16C6X
0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx
0000 0000
1111 1111
0000 0000
0000 0000
Value on
POR,
BOR
2
C bus may be taken
DS30234D-page 103
Value on all
other resets
0000 000u
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111