PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 39

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch)
FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch)
1997 Microchip Technology Inc.
bit7
bit7
bit 7-6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
bit 7:
bit 6:
bit 5-4:
bit 3:
bit 2:
bit 1:
bit 0:
PSPIE
R/W-0
R/W-0
—
Reserved: Always maintain these bits clear.
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Reserved: Always maintain this bit clear.
Unimplemented: Read as '0'
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
R/W-0
—
—
R/W-0
RCIE
U-0
—
R/W-0
TXIE
U-0
—
SSPIE
SSPIE
R/W-0
R/W-0
CCP1IE
CCP1IE
R/W-0
R/W-0
TMR2IE
TMR2IE
R/W-0
R/W-0
TMR1IE
TMR1IE
R/W-0
R/W-0
bit0
bit0
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
read as ‘0’
read as ‘0’
PIC16C6X
DS30234D-page 39