PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 98

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
11.4.4
The I
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbi-
tration and synchronization occur.
11.4.4.1
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 11-22), and turns off its data output stage. A
master which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 11-22: MULTI-MASTER
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning mas-
ter-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condi-
Care needs to be taken to ensure that these conditions
do not occur.
DS30234D-page 98
tion
DATA 2
SDA
SCL
DATA 1
2
C protocol allows a system to have more than
MULTI-MASTER
ARBITRATION
ARBITRATION
(TWO MASTERS)
transmitter 1 loses arbitration
DATA 1 SDA
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.2.4.2 Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a wired-
AND connection to the SCL line. A high to low transition
on the SCL line causes the concerned devices to start
counting off their low period. Once a device clock has
gone low, it will hold the SCL line low until its SCL high
state is reached. The low to high transition of this clock
may not change the state of the SCL line, if another
device clock is still within its low period. The SCL line is
held low by the device with the longest low period.
Devices with shorter low periods enter a high wait-
state, until the SCL line comes high. When the SCL line
comes high, all devices start counting off their high
periods. The first device to complete its high period will
pull the SCL line low. The SCL line high time is deter-
mined by the device with the shortest high period,
Figure 11-23.
FIGURE 11-23: CLOCK SYNCHRONIZATION
SCL
CLK
CLK
1
2
counter
reset
state
1997 Microchip Technology Inc.
wait
start counting
HIGH period