PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 84

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
11.2
This section contains register definitions and opera-
tional characteristics of the SPI module for the
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63,
PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64,
PIC16C65, PIC16C65A, PIC16CR65.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
DS30234D-page 84
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
U-0
—
SPI Mode for PIC16C62/62A/R62/63/
R63/64/64A/R64/65/65A/R65
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
U-0
—
D/A
2
R-0
C mode only)
2
2
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
2
C modes)
R-0
P
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
2
C mode only)
2
C mode only)
R-0
S
2
C mode only)
R/W
R-0
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’