PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 118

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
12.3.2
Once Synchronous Mode is selected, reception is
enabled
(RCSTA<5>) bit or enable bit CREN (RCSTA<4>).
Data is sampled on the DT pin on the falling edge of the
clock. If enable bit SREN is set, then only a single word
is received. If enable bit CREN is set, the reception is
continuous until bit CREN is cleared. If both the bits are
set then bit CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit, OERR
(RCSTA<1>) is set. The word in the RSR register will
be lost. The RCREG register can be read twice to
retrieve the two bytes in the FIFO. Overrun error bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
OERR if it is set. The 9th receive bit is buffered the
same way as the receive data. Reading the RCREG
register will load bit RX9D with a new value. Therefore
it is essential for the user to read the RCSTA register
before reading the RCREG register in order not to lose
the old RX9D bit information.
TABLE 12-9:
DS30234D-page 118
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
by
Name
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
setting
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
either
(1)
(1)
Bit 6
RX9
TX9
(2)
(2)
enable
SREN CREN
TXEN
RCIF
RCIE
Bit 5
bit
SYNC
Bit 4
TXIF
TXIE
SREN
SSPIF
SSPIE
Bit 3
—
—
CCP1IF
CCP1IE
Steps to follow when setting up Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set enable bit
SREN. For continuous reception set enable bit
CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
enable bit CREN.
TMR2IE
TMR2IF
OERR
TRMT
Bit 1
TMR1IE
TMR1IF
RX9D
TX9D
Bit 0
1997 Microchip Technology Inc.
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
POR,
BOR
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
all other
Resets