PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 34

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
TABLE 4-6:
DS30234D-page 34
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch-
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch-
19Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Note 1: These registers can be addressed from any bank.
Address Name
Bank 2
Bank 3
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1,2)
(1)
(1,2)
(1)
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
INDF
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter. (PC<12:8>)
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
RBPU
Bit 7
IRP
GIE
IRP
GIE
—
—
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
Write Buffer for the upper 5 bits of the Program Counter
T0SE
Bit 4
INTE
INTE
TO
TO
RBIE
RBIE
Bit 3
PSA
PD
PD
Bit 2
T0IF
T0IF
PS2
Z
Z
Bit 1
INTF
INTF
PS1
DC
DC
Bit 0
RBIF
RBIF
PS0
1997 Microchip Technology Inc.
C
C
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
Value on
all other
resets
—
—
—
—
—
—
—
—
—
—
(3)