PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 138

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
13.5.1
External interrupt on RB0/INT pin is edge triggered:
either rising if edge select bit INTEDG (OPTION<6>) is
set, or falling, if bit INTEDG is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). The INTF bit
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake the processor from SLEEP, if enable bit INTE
was set prior to going into SLEEP. The status of global
enable bit GIE decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 13.8 for details on SLEEP mode.
FIGURE 13-19: INT PIN INTERRUPT TIMING
DS30234D-page 138
INSTRUCTION FLOW
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT(3)
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
Note 1: INTF flag is sampled here (every Q1).
INT INTERRUPT
on
2: Interrupt latency = 3T
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width spec of INT pulse, refer to AC specs.
5: INTF can to be set anytime during the Q4-Q1 cycles.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
1
Q2
PC
Q3
4
pin,
Q4
5
CY
for synchronous interrupt and 3-4T
Q1
flag
Inst (PC+1)
Inst (PC)
Q2
1
bit
PC+1
Q3
INTF
Q4
Interrupt Latency (2)
Q1
Dummy Cycle
Q2
PC+1
13.5.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 7.0).
13.5.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 5.2).
—
Note:
Q3
CY
for asynchronous interrupt.
Q4
TMR0 INTERRUPT
PORTB INTERRUPT ON CHANGE
For the PIC16C61/62/64/65, if a change on
the I/O pin should occur when the read
operation is being executed (start of the Q2
cycle), then flag bit RBIF may not get set.
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
00h) in the TMR0 register will set
Q3
1997 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4