PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 88

• Manufacturer Part Number: PIC16LC65-04I/L
• Description: IC MIC CTL 4K LP OTP IT 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC65-04I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Data Converters: -

PIC16C6X
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set the for synchro-
nous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. If the SS pin is taken low without resetting
SPI mode, the transmission will continue from the
FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL
FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL
TABLE 11-1:
DS30234D-page 88
Address Name
0Bh,8Bh INTCON
0Ch
8Ch
13h
14h
85h
87h
94h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI
Note 1: These bits are associated with the USART which is implemented on the PIC16C63/R63/65/65A/R65 only.
SCK
(CKP = 0)
SCK
(CKP = 1)
2: PSPIF and PSPIE are reserved on the PIC16C62/62A/R62/63/R63, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
SCK
(CKP = 0)
SCK
(CKP = 1)
SS
SSPIF
SDO
mode.
SSPIF
SDI
PIR1
PIE1
SSPBUF
SSPCON
TRISA
TRISC
SSPSTAT
SDO
SDI
REGISTERS ASSOCIATED WITH SPI OPERATION
Synchronous Serial Port Receive Buffer/Transmit Register
PORTC Data Direction Register
PSPIF
PSPIE
WCOL
Bit 7
GIE
—
—
bit7
(2)
(2)
bit7
bit7
SSPOV SSPEN
bit7
Bit 6
PEIE
(3)
(3)
—
—
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
bit6
PORTA Data Direction Register
RCIE
RCIF
bit6
Bit 5
T0IE
D/A
(1)
(1)
bit5
TXIE
TXIF
Bit 4
INTE
CKP
bit5
P
(1)
(1)
bit4
SSPM3 SSPM2
SSPIF
SSPIE
RBIE
Bit 3
S
bit4
point at which it was taken high. External pull-up/
pull-down resistors may be desirable, depending on the
application.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
bit3
Bit 2
T0IF
R/W
bit3
SSPM1
Bit 1
INTF
bit2
UA
bit2
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
BF
bit1
1997 Microchip Technology Inc.
bit1
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
--00 0000 --00 0000
1111 1111 1111 1111
Value on:
POR,
BOR
bit0
bit0
bit0
bit0
Value on
all other
Resets