PIC16LC65-04I/L Microchip Technology, PIC16LC65-04I/L Datasheet - Page 77

IC MIC CTL 4K LP OTP IT 44PLCC

PIC16LC65-04I/L

Manufacturer Part Number
PIC16LC65-04I/L
Description
IC MIC CTL 4K LP OTP IT 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet

Specifications of PIC16LC65-04I/L

Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Data Converters
-
10.0
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave duty cycle register. Both the CCP1 and
CCP2 modules are identical in operation, with the
exception of the operation of the special event trigger.
Table 10-1 and Table 10-2 show the resources and
interactions of the CCP modules(s). In the following
sections, the operation of a CCP module is described
with respect to CCP1. CCP2 operates the same as
CCP1, except where noted.
CCP1 module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 10-2:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP2
CCPx Mode CCPy Mode
Capture
Capture
Compare
PWM
PWM
PWM
1997 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULE(s)
Capture
Compare
Compare
PWM
Capture
Compare
INTERACTION OF TWO CCP MODULES
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
None
None
CCP2 module:
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
For use of the CCP modules, refer to the Embedded
Control Handbook, “Using the CCP Modules” (AN594).
TABLE 10-1:
Interaction
CCP Mode
Compare
Capture
PWM
CCP MODE - TIMER
RESOURCE
PIC16C6X
Timer Resource
DS30234D-page 77
Timer1
Timer1
Timer2

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