SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet
SI1015-A-GM
Specifications of SI1015-A-GM
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SI1015-A-GM Summary of contents
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Ultra Low Power: 0.9 to 3.6 V Operation - Typical sleep mode current < 0.1 µA; retains state and RAM contents over full supply range; fast wakeup of < 2 µs Less than 600 nA with RTC running - Less ...
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Si1010/1/2/3/4/5 Table of Contents 1. System Overview ..................................................................................................... 20 1.1. Typical Connection Diagram ............................................................................. 24 1.2. CIP-51™ Microcontroller Core .......................................................................... 25 1.2.1. Fully 8051 Compatible .............................................................................. 25 1.2.2. Improved Throughput................................................................................ 25 1.2.3. Additional Features ................................................................................... 25 1.3. Port Input/Output ............................................................................................... ...
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Voltage Reference Electrical Specifications .................................................. 101 6. Programmable Current Reference (IREF0).......................................................... 102 6.1. PWM Enhanced Mode..................................................................................... 102 6.2. IREF0 Specifications ....................................................................................... 103 7. Comparators........................................................................................................... 104 7.1. Comparator Inputs........................................................................................... 104 7.2. Comparator Outputs ........................................................................................ 105 7.3. Comparator Response Time ........................................................................... ...
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Si1010/1/2/3/4/5 13.5. Flash Write and Erase Guidelines ................................................................. 151 13.5.1. VDD Maintenance and the VDD Monitor .............................................. 151 13.5.2. PSWE Maintenance .............................................................................. 151 13.5.3. System Clock ........................................................................................ 152 13.6. Minimizing Flash Read Current ..................................................................... 153 14. Power Management ............................................................................................. 157 ...
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Software Reset .............................................................................................. 192 19. Clocking Sources................................................................................................. 194 19.1. Programmable Precision Internal Oscillator .................................................. 195 19.2. Low Power Internal Oscillator........................................................................ 195 19.3. External Oscillator Drive Circuit..................................................................... 195 19.3.1. External Crystal Mode........................................................................... 195 19.3.2. External RC Mode................................................................................. 197 19.3.3. External ...
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Si1010/1/2/3/4/5 22. EZRadioPRO Serial Interface (SPI1)................................................................... 239 22.1. Signal Descriptions........................................................................................ 240 22.1.1. Master Out, Slave In (MOSI)................................................................. 240 22.1.2. Master In, Slave Out (MISO)................................................................. 240 22.1.3. Serial Clock (SCK) ................................................................................ 240 22.1.4. Slave Select (NSS) ............................................................................... 240 22.2. SPI Master ...
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Preamble Detector ................................................................................ 276 23.6.7. Preamble Length................................................................................... 276 23.6.8. Invalid Preamble Detector..................................................................... 277 23.6.9. Synchronization Word Configuration..................................................... 277 23.6.10. Receive Header Check ....................................................................... 278 23.6.11. TX Retransmission and Auto TX......................................................... 278 23.7. RX Modem Configuration .............................................................................. 279 23.7.1. Modem ...
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Si1010/1/2/3/4/5 25. UART0 ................................................................................................................... 318 25.1. Enhanced Baud Rate Generation.................................................................. 319 25.2. Operational Modes ........................................................................................ 319 25.2.1. 8-Bit UART ............................................................................................ 320 25.2.2. 9-Bit UART ............................................................................................ 320 25.3. Multiprocessor Communications ................................................................... 321 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 325 26.1. ...
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Register Descriptions for PCA0..................................................................... 373 29. C2 Interface .......................................................................................................... 379 29.1. C2 Interface Registers................................................................................... 379 29.2. C2 Pin Sharing .............................................................................................. 382 Document Change List.............................................................................................. 383 Contact Information................................................................................................... 384 Si1010/1/2/3/4/5 Rev. 1.0 9 ...
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... Figure 1.3. Si1012 Block Diagram ........................................................................... 22 Figure 1.4. Si1013 Block Diagram ........................................................................... 22 Figure 1.5. Si1014 Block Diagram ........................................................................... 23 Figure 1.6. Si1015 Block Diagram ........................................................................... 23 Figure 1.7. Si1012/3 RX/TX Direct-tie Application Example .................................... 24 Figure 1.8. Si1010/1 Antenna Diversity Application Example ................................. 24 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 26 Figure 1 ...
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Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111 Figure 8.1. CIP-51 Block Diagram ......................................................................... 114 Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123 Figure 9.2. Flash Program Memory Map ............................................................... 124 Figure 13.1. Flash Program Memory Map (16 kB and 8 ...
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Si1010/1/2/3/4/5 Figure 23.18. Manchester Coding Example .......................................................... 276 Figure 23.19. Header ............................................................................................. 278 Figure 23.20. POR Glitch Parameters ................................................................... 279 Figure 23.21. General Purpose ADC Architecture ................................................ 282 Figure 23.22. Temperature Ranges using ADC8 .................................................. 284 Figure 23.23. WUT Interrupt ...
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Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 356 Figure 28.1. PCA Block Diagram ........................................................................... 360 Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 362 Figure 28.3. PCA Interrupt Block Diagram ............................................................ 363 Figure 28.4. PCA Capture Mode Diagram ............................................................. ...
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Si1010/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 31 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 .................................................. 32 Table 3.2. QFN-42 Package Dimensions ................................................................ 39 Table 3.3. PCB Land Pattern ................................................................................... 43 Table 4.1. Absolute Maximum Ratings .................................................................... ...
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Table 20.3. SmaRTClock Bias Settings ................................................................ 212 Table 21.1. Port I/O Assignment for Analog Functions ......................................... 221 Table 21.2. Port I/O Assignment for Digital Functions ........................................... 222 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 222 ...
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Si1010/1/2/3/4/5 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 85 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 86 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 87 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 88 ...
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SFR Definition 14.2. PMU0MD: Power Management Unit Mode ................................ 164 SFR Definition 14.3. PCON: Power Management Control Register ........................... 165 SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 169 SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 170 SFR Definition 15.3. ...
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Si1010/1/2/3/4/5 SFR Definition 21.19. P2MDOUT: Port2 Output Mode ............................................... 238 SFR Definition 21.20. P2DRV: Port2 Drive Strength .................................................. 238 SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 244 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 245 SFR Definition 22.3. SPI1CKR: SPI ...
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C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 381 C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 381 Si1010/1/2/3/4/5 Rev. 1.0 19 ...
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Si1010/1/2/3/4/5 1. System Overview Si1010/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. ® 240–960 MHz EZRadioPRO transceiver Single/Dual Battery operation with ...
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CIP-51 8051 Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 512 Byte XRAM Hardware C2D Engine VDD VREG SYSCLK GND Precision 24.5 MHz Oscillator Low Power 20 MHz ...
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Si1010/1/2/3/4/5 CIP-51 8051 Power On Controller Core Reset/PMU 16k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 512 Byte XRAM Hardware C2D VDD VREG GND Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator ...
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... VBAT Low Power Converter 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.6. Si1015 Block Diagram Si1010/1/2/3/4/5 Analog Peripherals 6-bit IREF0 IREF External Internal VREF VREF VDD VREF A 12/10-bit Temp M 75/300 ksps Sensor ...
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Si1010/1/2/3/4/5 1.1. Typical Connection Diagram The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference ...
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CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible The Si1010/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The ...
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Si1010/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 12 I/O pins. Port pins are organized as three byte-wide ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to ...
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Serial Ports The Si1010/1/2/3/4/5 Family includes an SMBus/I rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hard- ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU ...
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Si1010/1/2/3/4/5 1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1010/1/2/3/4/5 devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autono- ...
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P0.0 P1.6* Temp Sensor VBAT Digital Supply VDD_MCU/DC+ *P1.0 – P1.3 are not available as device pins Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with ...
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Si1010/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 ...
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... Si1013-A- 768 P Si1014-A- 768 P Si1015-A- 768 P *The ‘F9xx Plus features are a set of enhancements that allow greater power efficiency and increased functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO, VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The ‘F9xx Plus features are described in detail in “ ...
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Si1010/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 Name Pin Number Si1010/1 Si1014/5 Si1012/3 VDD_MCU 38 — GND_MCU 37 — — VBAT 41 GND — 38 VBAT- DCEN — 40 VDD_MCU / — 39 DC+ ...
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Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Type Si1010/1 Si1014/5 Si1012/3 RST I/O C2CK D I/O P2. I/O C2D D I/O XTAL3 XTAL4 ...
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Si1010/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Si1010/1 Si1014/5 Si1012 CNVSTR P0 IREF0 ...
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Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Type Si1010/1 Si1014/5 Si1012/3 NC 14, 20, 14, 20 SDN RXp RXn 19 19 ...
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Si1010/1/2/3/4/5 XTAL3 1 N.C. 2 N.C. 3 P1.6 4 P1.5 5 P1.4 6 N.C. 7 N.C. 8 N.C. 9 N.C. 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) 36 GND_M CU Si1010/1/2/3 ...
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P2.7/C2D 1 XTAL4 2 XTAL3 3 P1.6 4 P1.5 5 P1.4 6 N.C. 7 N.C. 8 N.C. 9 N.C. 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.2. Si1004/5 Pinout Diagram (Top View) Si1010/1/2/3/4/5 GND_M CU Si1014/5 Top ...
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Si1010/1/2/3/4/5 Figure 3.3. QFN-42 Package Drawing 38 Rev. 1.0 ...
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Table 3.2. QFN-42 Package Dimensions Dimension Min Typ Max A 0.60 0.65 0.70 b 0.20 0.25 0.30 D 5.00 BSC D1 3.00 BSC D2 4.25 BSC D3 3.11 3.16 3.21 D4 2.68 2.73 2.78 e 0.50 BSC E 7.00 BSC ...
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Si1010/1/2/3/4/5 Figure 3.4. Typical QFN-42 Landing Diagram 40 Rev. 1.0 ...
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Figure 3.5. VIA Placement and Keepout Region Si1010/1/2/3/4/5 Rev. 1.0 41 ...
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Si1010/1/2/3/4/5 Figure 3.6. Typical PCB Stencil Diagram 42 Rev. 1.0 ...
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Dimension C1 X1 (27x) Y1 (27x (15x) Y2 (15x General All dimensions shown are in millimeters (mm) unless otherwise noted. 1. This land pattern design is based on ...
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Si1010/1/2/3/4/5 4. Electrical Characteristics In Section 4.1 and Section 4.2, “ the VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifica- tions in these two sections do not apply to the EZRadioPRO peripheral. In ...
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Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in ...
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Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. ...
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Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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F < 14 MHz 4100 4000 Oneshot Enabled 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 200 uA/MHz 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 215 uA/MHz ...
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Si1010/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 ...
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Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC Si1010/1/2/3/4/5 Load Current (mA) Rev. 1.0 51 ...
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Si1010/1/2/3/4/5 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC Rev. 1.0 ...
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Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC Si1010/1/2/3/4/5 Load current (mA) Rev. 1.0 53 ...
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Si1010/1/2/3/4/5 Figure 4.6. Typical One-Cell Suspend Mode Current 54 Rev. 1.0 ...
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Table 4.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage High Drive Strength, PnDRV IOH = –3 mA, Port I/O push-pull IOH = ...
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Si1010/1/2/3/4/5 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.7. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode) ...
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Typical VOH (High Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 ...
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Si1010/1/2/3/4/5 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.9. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD ...
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Typical VOL (High Drive Mode) 0.5 VDD = 1.8V 0.4 VDD = 1.5V VDD = 1.2V 0.3 VDD = 0.9V 0.2 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 0.4 0.3 VDD = ...
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Si1010/1/2/3/4/5 Table 4.4. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD/DC+ Monitor Thresh- ...
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Table 4.5. Power Management Electrical Specifications V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics V = ...
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Si1010/1/2/3/4/5 Table 4.9. SmaRTClock Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Oscillator Frequency (LFO) Table 4.10. ADC0 Electrical Characteristics V = 1.8 to 3.6V V, ...
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Table 4.10. ADC0 Electrical Characteristics (Continued 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter Analog Inputs ADC Input Voltage Range Single Ended (AIN+ – GND) Absolute Pin Voltage with respect to GND Sampling ...
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Si1010/1/2/3/4/5 Table 4.12. Voltage Reference Electrical Characteristics V = 1 +85 °C unless otherwise specified. – DD Parameter Internal High Speed Reference (REFSL[1:0] = 11) Output Voltage VREF Turn-on Time Supply Current Internal Precision Reference ...
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Table 4.13. IREF0 Electrical Characteristics V = 1 +85 °C, unless otherwise specified. – DD Parameter Static Performance 1 Resolution Output Compliance Range High Current Mode, Source Integral Nonlinearity Differential Nonlinearity Offset Error 2 Full ...
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Si1010/1/2/3/4/5 Table 4.14. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 2 1 Response Time: * Mode ...
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Table 4.14. Comparator Electrical Characteristics (Continued 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis 3 ...
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Si1010/1/2/3/4/5 Table 4.16. DC-DC Converter (DC0) Electrical Characteristics –40 to +85 °C unless otherwise specified. VBAT = 0.9 to 1.8 V, Parameter Input Voltage Range Input Inductor Value Input Inductor Current Rating Inductor DC Resistance Input Capacitor Value Output ...
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EZRadioPRO Electrical Characteristics Table 4.17. DC Characteristics Parameter Symbol Supply Voltage V DD Range Power Saving Modes I Shutdown I Low Power Digital Regulator ON (Register Standby values retained) and Main Digital Regula Oscillator and Low ...
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Si1010/1/2/3/4/5 Table 4.18. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS ...
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Table 4.19. Receiver AC Electrical Characteristics Parameter Symbol RX Frequency Range Sensitivity P RX_2 P RX_40 P RX_100 P RX_125 P RX_OOK 3 RX Channel Bandwidth BW BER Variation vs Power P RX_RES 3 Level 3 ...
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Si1010/1/2/3/4/5 Table 4.20. Transmitter AC Electrical Characteristics Parameter Symbol TX Frequency Range FSK Data Rate DR FSK 2 OOK Data Rate DR OOK Modulation Deviation Δf1 Δf2 Modulation Deviation Δf RES 2 Resolution Output Power Range— ...
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Table 4.21. Auxiliary Block Specifications Parameter Symbol Temperature Sensor Accuracy Temperature Sensor Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock Output ...
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Si1010/1/2/3/4/5 Table 4.22. Digital IO Specifications (nIRQ) Parameter Symbol Rise Time T RISE Fall Time T FALL Input Capacitance C IN Logic High Level Input V IH Voltage Logic Low Level Input V IL Voltage Input Current I IN Logic ...
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Table 4.24. Absolute Maximum Ratings Parameter V to GND DD Instantaneous V to GND on TX Output Pin RF-peak Sustained V to GND on TX Output Pin RF-peak Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power ...
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Si1010/1/2/3/4/5 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral Production Test Conditions +25 °C +3.3 VDC DD Sensitivity measured at 919 MHz TX output power measured at 915 MHz External ...
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SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on Si1010/1/2/3/4/5 devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation- register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also ...
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Si1010/1/2/3/4/5 5.1. Output Code Formatting The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting ...
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Modes of Operation ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SAR- CLK divided version of the system clock when Burst Mode is disabled (BURSTEN = 0 ...
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Si1010/1/2/3/4/5 5.2.2. Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 4.10. The AD0TM bit in register ADC0CN con- ...
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Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver- sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 16, ...
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Si1010/1/2/3/4/5 5.2.4. Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, ...
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Mode Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the 8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock ...
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Si1010/1/2/3/4/5 Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65V High-Speed VREF 8 bit 8.17 MHz Highest nominal SAR (24 clock frequency Total number of conversion clocks 11 required 1.5 us Total tracking ...
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SFR Definition 5.1. ADC0CN: ADC0 Control Bit 7 6 AD0EN BURSTEN AD0INT Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xE8; bit-addressable; Bit Name 7 AD0EN ADC0 Enable. 0: ADC0 Disabled (low-power shutdown). 1: ...
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Si1010/1/2/3/4/5 SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK ...
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SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration Bit 7 6 Name AD012BE AD0AE R/W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBA Bit Name 7 AD012BE ADC0 12-Bit Mode Enable. Enables 12-bit Mode. 0: 12-bit ...
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Si1010/1/2/3/4/5 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 AD0LPM Name R/W R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 AD0LPM ADC0 Low Power Mode Enable. Enables Low ...
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SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time Bit 7 6 Reserved Name R R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBD Bit Name 7:6 Reserved Read = 0b; Write = Must Write 0b. ...
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Si1010/1/2/3/4/5 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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Si1010/1/2/3/4/5 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than ...
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Window Detector In Single-Ended Mode Figure 5.5 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a ...
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Si1010/1/2/3/4/5 5.7. ADC0 Analog Multiplexer ADC0 on Si1010/1/2/3/4/5 has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the ...
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SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBB Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AD0MX AMUX0 ...
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Si1010/1/2/3/4/5 5.8. Temperature Sensor An on-chip temperature sensor is included on the Si1010/1/2/3/4/5 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select ...
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Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame- ters that affect ADC measurement, in particular the voltage reference value, will also affect temper- ature measurement. A single-point offset measurement of the temperature ...
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Si1010/1/2/3/4/5 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant ...
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Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, one of two internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference MUX allows ...
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Si1010/1/2/3/4/5 5.10. External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref- erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended ...
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SFR Definition 5.15. REF0CN: Voltage Reference Control Bit 7 6 REFGND Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xD1 Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND Analog ...
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Si1010/1/2/3/4/5 6. Programmable Current Reference (IREF0) Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 ...
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SFR Definition 6.2. IREF0CF: Current Reference Configuration Bit 7 6 PWMEN Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xB9 Bit Name 7 PWMEN PWM Enhanced Mode Enable. Enables the PWM Enhanced Mode. Only ...
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Si1010/1/2/3/4/5 7. Comparators Si1010/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi- cally, but may differ in their ability to ...
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Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. The ...
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Si1010/1/2/3/4/5 7.3. Comparator Response Time Comparator response time may be configured in software via the CPTnMD registers described on “CPT0MD: Comparator 0 Mode Selection” on page 108 and “CPT1MD: Comparator 1 Mode Selection” on page 110. Four response time settings ...
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Comparator Register Descriptions The SFRs used to enable and configure the comparators are described in the following register descrip- tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From ...
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Si1010/1/2/3/4/5 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 CP0RIE Name R/W R Type 1 0 Reset SFR Page = All Pages; SFR Address = 0x9D Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 ...
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SFR Definition 7.3. CPT1CN: Comparator 1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Page= 0x0; SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. ...
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Si1010/1/2/3/4/5 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection Bit 7 6 CP1RIE Name R/W R Type 1 0 Reset SFR Page = 0x0; SFR Address = 0x9C Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused ...
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Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on Si1010/1/2/3/4/5 devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0– are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- are ...
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Si1010/1/2/3/4/5 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select Bit 7 6 CMX0N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input ...
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SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select Bit 7 6 CMX1N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9E Bit Name 7:4 CMX1N Comparator1 Negative Input Selection. Selects the negative input channel ...
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Si1010/1/2/3/4/5 8. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...
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With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. ...
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Si1010/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A ...
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Si1010/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement ...
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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by ...
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Si1010/1/2/3/4/5 SFR Definition 8.1. DPL: Data Pointer Low Byte Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x82 Bit Name 7:0 DPL[7:0] Data Pointer Low. The DPL register is the low byte ...
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SFR Definition 8.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the ...
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Si1010/1/2/3/4/5 SFR Definition 8.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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Si1010/1/2/3/4/5 Reserved Area Lock Byte Page Si1010/2/4 Si1011/3/5 Flash Memory Space (SFLE=1) 0x01FF Scratchpad (Data Only) 0x0000 Figure 9.2. Flash Program Memory Map 9.1.1. MOVX Instruction and Program Memory The MOVX instruction in an 8051 device is typically used to ...
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General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen- eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these ...
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Si1010/1/2/3/4/5 10. On-Chip XRAM The Si1010/1/2/3/4/5 MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data ...
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SFR Definition 10.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAA Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 PGSEL XRAM ...
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Si1010/1/2/3/4/5 11. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the Si1010/1/2/3/4/5's resources and peripher- als. The CIP-51 controller core duplicates the ...
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SFR Paging To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple- mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in Table ...
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Si1010/1/2/3/4/5 SFR Definition 11.1. SFR Page: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA7 Bit Name 7:0 SFRPAGE[7:0] SFR Page. Specifies the SFR Page used when reading, writing, or ...
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Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page CRC0FLIP 0x95 0xF CRC0IN 0x93 0xF ...
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Si1010/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page PCA0CPH3 0xEE 0x0 PCA0CPH4 0xFE ...
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Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFRs highlighted in blue are only available on ‘F912 and ‘F902 devices. Register Address SFR Page SPI1CFG 0x84 0x0 SPI1CKR 0x85 0x0 ...
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Si1010/1/2/3/4/5 12. Interrupt Handler The Si1010/1/2/3/4/5 microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of ...
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Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be ...
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Si1010/1/2/3/4/5 Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 (INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B SmaRTClock Alarm 0x0043 ADC0 Window ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in the following register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid ...
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Si1010/1/2/3/4/5 SFR Definition 12.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. ...
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SFR Definition 12.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = don't care. 6 PSPI0 Serial ...
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Si1010/1/2/3/4/5 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit ...
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SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit ...
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Si1010/1/2/3/4/5 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = All Pages;SFR Address = 0xE7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. 3 ESPI1 ...
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SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. PSPI1 3 ...
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Si1010/1/2/3/4/5 12.6. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select ...
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SFR Definition 12.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input ...
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Si1010/1/2/3/4/5 13. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic ...
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Flash Erase Procedure The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire Flash page, perform the following steps: 1. Save ...
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Si1010/1/2/3/4/5 13.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE ...
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Table 13.1. Flash Security Summary Action Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or Erase locked pages (except page with Lock Byte) Read or Write page containing Lock Byte (if no pages are locked) ...
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... The part number can be determined by reading the value of the Flash byte at address 0x3FFE. The value of the Flash byte at address 0x3FFE can be decoded as follows: 0xD4—Si1010 0xD5—Si1011 0xD6—Si1012 0xD7—Si1013 0xD8—Si1014 0xD9—Si1015 150 Rev. 1.0 ...
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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...
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Si1010/1/2/3/4/5 and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. 9. Disable interrupts prior to setting ...
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Minimizing Flash Read Current The Flash memory in the Si1010/1/2/3/4/5 devices is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are suggestions to minimize Flash read current. 1. Use ...
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Si1010/1/2/3/4/5 SFR Definition 13.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Page =0x0; SFR Address = 0x8F Bit Name 7:3 Unused Read = 00000b, Write = don’t care. 2 SFLE Scratchpad ...
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SFR Definition 13.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and ...
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Si1010/1/2/3/4/5 SFR Definition 13.3. FLSCL: Flash Scale Bit 7 6 BYPASS Name R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7 Reserved Always Write BYPASS Flash Read Timing One-Shot ...
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Power Management Si1010/1/2/3/4/5 devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is ...
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Si1010/1/2/3/4/5 14.1. Normal Mode The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD_MCU/DC+, and the 1.8 V internal ...
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If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi- nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON ...
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Si1010/1/2/3/4/5 14.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci- ...
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Sleep Mode Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on ...
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Si1010/1/2/3/4/5 disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit. When the VBAT supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the VBAT supply monitor. In addition, any falling edge ...
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SFR Definition 14.1. PMU0CF: Power Management Unit Configuration Bit 7 6 SLEEP SUSPEND CLEAR Name W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB5 Bit Name Description 7 SLEEP Sleep Mode Select 6 SUSPEND Suspend ...
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Si1010/1/2/3/4/5 SFR Definition 14.2. PMU0MD: Power Management Unit Mode Bit 7 6 Name RTCOE WAKEOE MONDIS R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xB5 Bit Name 7 Buffered SmaRTClock Output Enable. RTCOE Enables the ...
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SFR Definition 14.3. PCON: Power Management Control Register Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x87 Bit Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE ...
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Si1010/1/2/3/4/5 15. Cyclic Redundancy Check Unit (CRC0) Si1010/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 ...
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The 16-bit Si1010/1/2/3/4/5 CRC algorithm can be described by the following code: unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input) { unsigned char i; #define POLY 0x1021 // Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with ...
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Si1010/1/2/3/4/5 15.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result ...
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SFR Definition 15.1. CRC0CN: CRC0 Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x92 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 CRC0SEL CRC0 Polynomial Select ...
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Si1010/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data ...
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SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control Bit 7 6 AUTOEN CRCDONE Name R/W R/W Type 0 1 Reset SFR Page = 0xF; SFR Address = 0x96 Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to ...
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Si1010/1/2/3/4/5 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x97 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 ...
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CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 ...
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Si1010/1/2/3/4/5 16. On-Chip DC-DC Converter (DC0) Si1014/5 devices include an on-chip dc-dc converter to allow operation from a single cell battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an ...
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Startup Behavior On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur- rent ...
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Si1010/1/2/3/4/5 16.2. High Power Applications The dc-dc converter is designed to provide the system with output power, however, it can safely provide up to 100 mW of output power without any risk of damage to the device. ...
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DC-DC Converter Enabled 0.9 to 1.8 V Supply Voltage (one-cell mode) DC-DC Converter Disabled 1.8 to 3.6 V Supply Voltage (two-cell mode) Figure 16.2. DC-DC Converter Configuration Options When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, ...
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Si1010/1/2/3/4/5 16.5. Minimizing Power Supply Noise To minimize noise on the power supply lines, the GND/VBAT- and GND_MCU/DC- pins should be kept separate, as shown in Figure 16.2; GND_MCU/DC- should be connected to the pc board ground plane. The large ...
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DC-DC Converter Behavior in Sleep Mode When the Si1014/5 devices are placed in Sleep mode, the dc-dc converter is disabled, and the VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO pins are ...
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Si1010/1/2/3/4/5 16.10. Low Power Mode Setting the LPEN bit in the DC0CF register will enable a Low Power Mode for the dc-dc converter. In Low Power Mode, the bias currents are substantially reduced, which can lead to an efficiency improvement ...
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DC-DC Converter Register Descriptions The SFRs used to configure the dc-dc converter are described in the following register descriptions. The reset values for these registers can be used as-is in most systems; therefore, no software intervention or initialization is ...
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Si1010/1/2/3/4/5 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration Bit 7 6 LPEN CLKDIV[1:0] Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0x96 Bit Name 7 LPEN Low Power Mode Enable. Enables the dc-dc low ...
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SFR Definition 16.3. DC0MD: DC-DC Mode Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x94 Bit Name 7:4 Unused Read = 0000b, Write = don’t care. 3 BYPFLG Bypass Indicator. Indicates ...
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Si1010/1/2/3/4/5 17. Voltage Regulator (VREG0) Si1010/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD_MCU/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined ...
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Si1010/1/2/3/4/5 VDD_MCU/DC+ Comparator 0 Px C0RSEF Px.x SmaRTClock RTC0RE Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler 18.1. Power-On (VBAT Supply Monitor) Reset During power-up, the device is held in a reset ...
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V POR 0.6 ~0.5 See specification table for min/max voltages. RST Logic HIGH Logic LOW Figure 18.2. Power-Fail Reset Timing Diagram Si1010/1/2/3/4/5 T PORDelay Power-On Power-On Reset Reset Rev. 1.0 VBAT t T PORDelay 187 ...
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Si1010/1/2/3/4/5 18.2. Power-Fail (VDD_MCU/DC+ Supply Monitor) Reset Si1010/1/2/3/4/5 devices have a VDD_MCU/DC+ Supply Monitor that is enabled and selected as a reset source after each power-on or power-fail reset. When enabled and selected as a reset source, any power down ...
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Important Notes: The Power-on Reset (POR) delay is not incurred after a VDD_MCU/DC+ supply monitor reset. See Section “4. Electrical Characteristics” on page 44 for complete electrical characteristics of the VDD_MCU/DC+ monitor. Software should take care not to inadvertently ...
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Si1010/1/2/3/4/5 SFR Definition 18.1. VDM0CN: VDD_MCU/DC+ Supply Monitor Control Bit 7 6 VDMEN VDDSTAT VDDOK Name R/W R Type 1 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xFF Bit Name 7 VDMEN VDD_MCU/DC+ Supply Monitor Enable. This ...
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External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the ...
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Si1010/1/2/3/4/5 The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. 18.8. SmaRTClock (Real Time Clock) Reset The SmaRTClock can generate a system reset on two events: SmaRTClock ...
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SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 RTC0RE FERROR C0RSEF Name R/W R Type Varies Varies Varies Reset SFR Page = 0x0; SFR Address = 0xEF. Bit Name Description 7 RTC0RE SmaRTClock Reset Enable and Flag 6 FERROR ...
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Si1010/1/2/3/4/5 19. Clocking Sources Si1010/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the ...
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Poll for CLKRDY > 1. 19.1. Programmable Precision Internal Oscillator All Si1010/1/2/3/4/5 devices include a programmable precision internal oscillator that may be selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section ...
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Si1010/1/2/3/4/5 Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces ...
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External RC Mode network is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for ...
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Si1010/1/2/3/4/5 3. Poll for XTLVLD => Switch the system clock to the external oscillator. 19.3.3. External Capacitor Mode If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option ...
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Special Function Registers for Selecting and Configuring the System Clock The clocking sources on Si1010/1/2/3/4/5 devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page ...
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Si1010/1/2/3/4/5 SFR Definition 19.1. CLKSEL: Clock Select Bit 7 6 CLKRDY CLKDIV[2:0] Name R R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA9 Bit Name 7 CLKRDY System Clock Divider Clock Ready Flag. 0: The ...