SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 204

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
Table 20.1. SmaRTClock Internal Registers
20.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Reg-
ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric-
tions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes
are written, or an indirect register read or write is attempted while the interface is locked, the SmaRTClock
interface will be disabled, and the RTC0ADR and RTC0DAT registers will become inaccessible until the
next system reset. Once the SmaRTClock interface is unlocked, software may perform any number of
accesses to the SmaRTClock registers until the interface is re-locked or the device is reset. Any write to
RTC0KEY while the SmaRTClock interface is unlocked will re-lock the interface.
Reading the RTC0KEY register at any time will provide the SmaRTClock Interface status and will not inter-
fere with the sequence that is being written. The RTC0KEY register description in SFR Definition 20.1 lists
the definition of each status code.
20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A SmaRT-
Clock Write operation is initiated by writing to the RTC0DAT register. Below is an example of writing to a
SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
204
SmaRTClock
0x08–0x0B
0x00–0x03
Address
0x04
0x05
0x06
0x07
SmaRTClock
CAPTUREn SmaRTClock Capture
RTC0XCN
RTC0XCF
RTC0PIN
Register
RTC0CN
ALARMn
SmaRTClock Oscillator
Registers
SmaRTClock Control
Register
Control Register
SmaRTClock Oscillator
Configuration Register
SmaRTClock Pin
Configuration Register
SmaRTClock Alarm
Registers
Register Name
Rev. 1.0
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
Controls the operation of the SmaRTClock State
Machine.
Controls the operation of the SmaRTClock
Oscillator.
Note: Some bits in this register are only available on
Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
Forces XTAL3 and XTAL4 to be internally
shorted.
Note: This register also contains other reserved bits
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
‘F912 and ‘F902 devices.
which should not be modified.
Description