SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 12

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
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Figure 23.18. Manchester Coding Example .......................................................... 276
Figure 23.19. Header ............................................................................................. 278
Figure 23.20. POR Glitch Parameters ................................................................... 279
Figure 23.21. General Purpose ADC Architecture ................................................ 282
Figure 23.22. Temperature Ranges using ADC8 .................................................. 284
Figure 23.23. WUT Interrupt and WUT Operation ................................................. 287
Figure 23.24. Low Duty Cycle Mode ..................................................................... 288
Figure 23.25. RSSI Value vs. Input Power ............................................................ 290
Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 291
Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 292
Figure 24.1. SMBus Block Diagram ...................................................................... 297
Figure 24.2. Typical SMBus Configuration ............................................................ 298
Figure 24.3. SMBus Transaction ........................................................................... 299
Figure 24.4. Typical SMBus SCL Generation ........................................................ 301
Figure 24.5. Typical Master Write Sequence ........................................................ 310
Figure 24.6. Typical Master Read Sequence ........................................................ 311
Figure 24.7. Typical Slave Write Sequence .......................................................... 312
Figure 24.8. Typical Slave Read Sequence .......................................................... 313
Figure 25.1. UART0 Block Diagram ...................................................................... 318
Figure 25.2. UART0 Baud Rate Logic ................................................................... 319
Figure 25.3. UART Interconnect Diagram ............................................................. 320
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 320
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 321
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 321
Figure 26.1. SPI Block Diagram ............................................................................ 325
Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 327
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave 
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave 
Figure 26.5. Master Mode Data/Clock Timing ....................................................... 330
Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 330
Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 331
Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 335
Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 335
Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 336
Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 336
Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 341
Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 342
Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 343
Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 348
Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 349
Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 350
Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 354
Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 355
Mode Connection Diagram ................................................................ 327
Mode Connection Diagram ................................................................ 328
Rev. 1.0