SI1015-A-GM Silicon Laboratories Inc, SI1015-A-GM Datasheet - Page 186

• Manufacturer Part Number: SI1015-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1015-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1868-5

Si1010/1/2/3/4/5
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
V
Figure 18.3 plots the power-on and V
power-on reset delay (T
3.6 V).
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
The VBAT supply monitor can be disabled to save power by writing ‘1’ to the MONDIS (PMU0MD.5) bit.
When the VBAT supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the
VBAT supply monitor.
Note: Si1010/1/2/3 have the VBAT signal internally connected to VDD_MCU.
186
POR
BAT
Px.x
Px.x
. An additional delay occurs before the device is released from reset; the delay decreases as the
ramp time increases (V
before V
SmaRTClock
BAT
System
Clock
Comparator 0
reaches the V
RTC0RE
+
-
DD
PORDelay
ramp time is 3 ms; slower ramp times may cause the device to be released from reset
C0RSEF
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
POR
CIP-51
BAT
Handler
Core
) is typically 3 ms (V
VDD_MCU/DC+
level.
ramp time is defined as how fast V
WDT
PCA
EN
Figure 18.1. Reset Sources
DD
monitor reset timing. For valid ramp times (less than 3 ms), the
System Reset
Supply
Monitor
+
-
Rev. 1.0
Enable
BAT
= 0.9 V), 7 ms (V
(Software Reset)
SWRSF
(wired-OR)
Power Management
Block (PMU0)
'0'
Power On
Reset
VBAT
Illegal Flash
Reset
Operation
BAT
BAT
System Reset
Power-On Reset
*On Si1010/1/2/3 devices,
connected to VDD_MCU.
VBAT is internally
ramps from 0 V to V
= 1.8 V), or 15 ms (V
Funnel
Reset
BAT
settles above
RST
BAT
POR
).
=