S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 15

• Manufacturer Part Number: S25FL016K0XMFI011
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI011

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

September 8, 2010 S25FL016K_00_02
6.1.8
6.1.9
6.1.10
Erase/Program Suspend Status (SUS)
Security Register Lock Bits (LB3, LB2, LB1)
Quad Enable (QE)
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Spansion for details.
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/
Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah)
instruction as well as a power-down, power-up cycle.
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers are unlocked. LB[3:1] can be set to 1 individually using the
Write Status Register instruction. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# are enabled. When
the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# functions are disabled.
Note: If the WP# or HOLD# pins are tied directly to the power supply or ground during standard SPI or Dual
SPI operation, the QE bit should never be set to a 1.
SRP1
0
0
0
1
1
SRP0
D a t a
0
1
1
0
1
WP#
Status Register Protect 0
S h e e t
Erase/Write In Progress
X
X
X
0
1
Top/Bottom Protect
Write Enable Latch
Block Protect Bits
Software Protection
Hardware Protected
Hardware Unprotected
Power Supply Lock-
Down
One Time Program
Sector Protect
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
Status Register
Table 6.1 Status Register Protection Bits
( P r e l i m i n a r y )
Figure 6.1 Status Register 1
S25FL016K
(2)
SRP0
SRP0
S7
S7
WP# pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When WP# pin is low the Status Register locked and can not be
written to.
When WP# pin is high the Status register is unlocked and can be
written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again until
the next power-down, power-up cycle.
Status Register is permanently protected and can not be written
to.
SEC
SEC
S6
S6
S5
S5
TB
TB
BP2
BP2
S4
S4
BP1
BP1
S3
S3
Description
BP0
BP0
S2
S2
WEL BUSY
WEL BUSY
(1)
S1
S1
S0
S0
15