LPC1768FBD100 NXP Semiconductors, LPC1768FBD100 Datasheet - Page 5

• Manufacturer Part Number: LPC1768FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1768FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 64KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 512KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
5. Block diagram
LPC1769_68_67_66_65_64_63
Product data sheet
Fig 1.
RXD0/TXD0
MOSI/MISO
PCAP1[1:0]
2 × MAT0/1
2 × CAP0/1
8 × UART1
SCK/SSEL
PWM1[7:0]
P0 to
AD0[7:0]
SSEL1
MISO1
MOSI1
SDA0/1
RTCX1
RTCX2
SCL0/1
SCK1
RD1/2
P4
P0, P2
(1) Not available on all parts. See
VBAT
TD1/2
Block diagram
debug
port
HIGH-SPEED
OSCILLATOR
GPIO INTERRUPT CONTROL
RTC POWER DOMAIN
GPIO
32 kHz
BACKUP REGISTERS
I-code
bus
APB slave group 0
PIN CONNECT
CORTEX-M3
interface
12-bit ADC
TIMER 0/1
CAN1/2
TEST/DEBUG
UART0/1
JTAG
INTERFACE
I2C0/1
PWM1
SSP1
ARM
SPI0
WDT
D-code
bus
(1)
slave
Table
RTC
system
bus
All information provided in this document is subject to legal disclaimers.
2.
MULTILAYER AHB MATRIX
CONTROLLER
BRIDGE 0
LPC1769/68/67/
AHB TO
Rev. 6.01 — 11 March 2011
66/65/64/63
APB
DMA
master
slave
LPC1769/68/67/66/65/64/63
CONTROLLER
WITH DMA
ETHERNET
RMII pins
BRIDGE 1
AHB TO
master
APB
(1)
slave
CONTROLLER
DEVICE/OTG
WITH DMA
USB HOST/
USB PHY
USB pins
32-bit ARM Cortex-M3 microcontroller
APB slave group 1
QUADRATURE ENCODER
EXTERNAL INTERRUPTS
MOTOR CONTROL PWM
slave
SYSTEM CONTROL
master
(1)
slave
slave
= connected to DMA
TIMER2/3
RI TIMER
UART2/3
DAC
SSP0
I2S
I2C2
POWER CONTROL,
(1)
ACCELERATOR
SRAM 32/64 kB
(1)
XTAL2
GENERATION,
512/256/128 kB
FUNCTIONS
SYSTEM
FLASH
CLOCK
FLASH
XTAL1
clocks and
ROM
controls
RESET
002aad944
© NXP B.V. 2011. All rights reserved.
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
MCABORT
PHA, PHB
INDEX
RXD2/3
TXD2/3
3 × I2SRX
3 × I2STX
TX_MCLK
RX_MCLK
SCL2
SDA2
EINT[3:0]
AOUT
CLKOUT
4 × MAT2
2 × MAT3
2 × CAP2
2 × CAP3
SCK0
SSEL0
MISO0
MOSI0
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