UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 145

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KE2. Therefore, the relationship
between the CPU clock (f
Address: FFFBH
Symbol
PCC
Caution
Notes 1. Bit 5 is read-only.
Remarks 1. f
CSS
CLS
7
0
0
1
0
1
After reset: 01H
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock
Figure 6-3. Format of Processor Clock Control Register (PCC)
2. f
operation mode select register (OSCCTL)). See (3) Setting of operation mode for
subsystem clock pin.
Be sure to clear bits 3 and 7 to “0”.
XTSTART
Main system clock
Subsystem clock
CPU
XP
SUB
PCC2
Other than above
) and the minimum instruction execution time is as shown in Table 6-2.
:
0
0
0
0
1
0
0
0
0
1
6
: Subsystem clock oscillation frequency
Main system clock oscillation frequency
Note2
R/W
CHAPTER 6 CLOCK GENERATOR
PCC1
CLS
Note 1
<5>
User’s Manual U17260EJ6V0UD
0
0
1
1
0
0
0
1
1
0
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
CPU clock status
f
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
SUB
/2 (default)
/2
/2
/2
/2
2
3
4
3
0
CPU clock (f
PCC2
2
CPU
) selection
PCC1
1
PCC0
0
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