UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 158

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Subsystem clock (f
158
(when XT1 oscillation
oscillation clock (f
Internal reset signal
(when X1 oscillation
Internal high-speed
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
Note
Caution
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
<2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling high-
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
system clock (f
Power supply
voltage (V
High-speed
CPU clock
oscillator automatically starts oscillation.
speed oscillation clock.
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3
Example of controlling subsystem clock).
selected)
selected)
4.
software settings.
stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed
system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
6.6.3 Example of controlling subsystem clock).
DD
SUB
0 V
RH
XH
It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK and EXCLKS pins is used.
Figure 6-13. Clock Generator Operation When Power Supply Voltage Is Turned On
)
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
)
)
)
<1>
(When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
Waiting for oscillation accuracy
The internal high-speed oscillation clock and high-speed system clock can be
stabilization (86 to 361 s)
2.7 V (TYP.)
CHAPTER 6 CLOCK GENERATOR
Starting X1 oscillation
is set by software.
User’s Manual U17260EJ6V0UD
<3>
<2>
Starting XT1 oscillation
is set by software.
µ
Reset processing
<4>
(11 to 45 s)
oscillation stabilization time:
Internal high-speed
oscillation clock
2
<4>
11
/f
µ
X1 clock
X
to 2
16
/f
X
Note
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock