UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 391

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(5) Data frame length during continuous transmission
When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by
two clocks of base clock from the normal value. However, the result of communication is not affected because
the timing is initialized on the reception side when the start bit is detected.
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is f
expression is satisfied.
Therefore, the data frame length during continuous transmission is:
FLstp = FL + 2/f
Data frame length = 11 × FL + 2/f
Start bit
FL
Figure 15-26. Data Frame Length During Continuous Transmission
XCLK6
Bit 0
FL
CHAPTER 15 SERIAL INTERFACE UART6
Bit 1
FL
XCLK6
1 data frame
User’s Manual U17260EJ6V0UD
Bit 7
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Start bit of
second byte
XCLK6
Bit 0
FL
, the following
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