UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 447

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
SDA0
SCL0
Remark
Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0
(IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0
(IICC0) to 1 before a stop condition is detected.
Figure 17-22 shows the communication reservation protocol.
SDA0
SPD0
SCL0
STD0
Hardware processing
Program processing
1
IIC0:
STT0:
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
2
Figure 17-21. Timing for Accepting Communication Reservations
3
Bit 1 of IIC control register 0 (IICC0)
IIC shift register 0
STT0 = 1
Communi-
cation
reservation
4
Figure 17-20. Communication Reservation Timing
5
CHAPTER 17 SERIAL INTERFACE IIC0
6
User’s Manual U17260EJ6V0UD
7
Standby mode
Generate by master device with bus mastership
8
9
Set SPD0
and
INTIIC0
Write to
IIC0
Set
STD0
1
2
3
4
5
447
6

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