UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 423

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

ACKE0
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• Reset
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• Reset
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• Reset
Notes 1. This flag’s signal is invalid when IICE0 = 0.
WTIM0
SPIE0
0
1
0
1
0
1
Notes 1, 2
Note 1
Note 1
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledge is generated regardless
of the set value.
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However, ACK is
invalid during address transfers and other than in expansion mode.
Figure 17-5. Format of IIC Control Register 0 (IICC0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
CHAPTER 17 SERIAL INTERFACE IIC0
Control of wait and interrupt request generation
User’s Manual U17260EJ6V0UD
Acknowledgment control
Condition for setting (SPIE0 = 1)
• Set by instruction
Condition for setting (WTIM0 = 1)
• Set by instruction
Condition for setting (ACKE0 = 1)
• Set by instruction
423