UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 602

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

28.2 Operation List
602
8-bit data
transfer
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
MOV
XCH
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 28 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17260EJ6V0UD
Bytes
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
Note 1
4
6
−
2
2
4
4
−
−
8
8
−
−
−
4
4
4
4
8
8
6
6
6
6
2
4
−
8
4
4
8
8
8
Clocks
Note 2
10
10
10
10
−
7
7
−
−
5
5
5
5
9
9
7
5
5
5
5
5
5
9
9
7
7
7
7
−
6
6
6
6
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
r ← A
A ← (saddr)
(saddr) ← A
A ← sfr
sfr ← A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
(HL) ← A
A ← (HL + byte)
(HL + byte) ← A
A ← (HL + B)
(HL + B) ← A
A ← (HL + C)
(HL + C) ← A
A ↔ r
A ↔ (saddr)
A ↔ (sfr)
A ↔ (addr16)
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A ↔ (HL + B)
A ↔ (HL + C)
CPU
) selected by the processor clock
Operation
Z AC CY
×
×
Flag
×
×
×
×