LPC1758FBD80 NXP Semiconductors, LPC1758FBD80 Datasheet - Page 20

• Manufacturer Part Number: LPC1758FBD80
• Description: IC, 32BIT MCU, ARM CORTEX, 100MHZ LQFP80
• Manufacturer: NXP Semiconductors

Specifications of LPC1758FBD80

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 52
• Ram Memory Size: 64KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1758_56_54_52_51_3
Product data sheet
7.12.2.1 Features
7.12.3.1 Features
7.12.2 USB host controller (LPC1758/56/54 only).
7.12.3 USB OTG controller (LPC1758/56/54 only).
7.13 CAN controller and acceptance filters
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of a register interface, a serial interface engine, and a DMA
controller. The register interface complies with the Open Host Controller Interface (OHCI)
specification.
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only
I
interface controls an external OTG transceiver.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
Remark: LPC1754/52/51 have only one CAN bus.
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C-bus interface to implement OTG dual-role device functionality. The dedicated I
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While USB is in the Suspend mode, the LPC1758/56/54/52/51 can enter one of the
reduced power modes and wake up on USB activity.
Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
OHCI compliant.
One downstream port.
Supports port power switching.
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
Rev. 03 — 19 November 2009
LPC1758/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2009. All rights reserved.
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C-bus
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