LPC1758FBD80 NXP Semiconductors, LPC1758FBD80 Datasheet - Page 35

• Manufacturer Part Number: LPC1758FBD80
• Description: IC, 32BIT MCU, ARM CORTEX, 100MHZ LQFP80
• Manufacturer: NXP Semiconductors

Specifications of LPC1758FBD80

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 52
• Ram Memory Size: 64KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1758_56_54_52_51_3
Product data sheet
CAUTION
7.30.2 Brownout detection
7.30.3 Code security (Code Read Protection - CRP)
7.30.4 APB interface
The LPC1758/56/54/52/51 include 2-stage monitoring of the voltage on the V
pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts reset to inactivate the
LPC1758/56/54/52/51 when the voltage on the V
reset prevents alteration of the flash as operation of the various elements of the chip
would otherwise become unreliable due to low voltage. The BOD circuit maintains this
reset down below 1 V, at which point the power-on reset circuitry maintains the overall
reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
This feature of the LPC1758/56/54/52/51 allows user to enable different levels of security
in the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Rev. 03 — 19 November 2009
LPC1758/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
DD(REG)(3V3)
pins falls below 2.65 V. This
© NXP B.V. 2009. All rights reserved.
DD(REG)(3V3)
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