MA160014 Microchip Technology, MA160014 Datasheet - Page 218

• Manufacturer Part Number: MA160014
• Description: MOD PLUG-IN 44PIN PIC18LF45K22
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of MA160014

• Accessory Type: Plug-In Module (PIM) - PIC18LF45K10
• Product: Microcontroller Modules
• Data Bus Width: 8 bit
• Core Processor: PIC18LF45K22
• Interface Type: I2C, SPI
• Operating Supply Voltage: 1.8 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM PIC18 Explorer, DM183032
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
15.3
The Inter-Integrated Circuit Bus (I
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
The I
• Serial Clock (SCLx)
• Serial Data (SDAx)
Figure 15-11
module when operating in I
Both the SCLx and SDAx connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 15-11
processors configured as master and slave devices.
The I
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
• Master Receive mode
• Slave Transmit mode
• Slave Receive mode
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDAx line while the SCLx line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
DS41412D-page 218
(master is transmitting data to a slave)
(master is receiving data from a slave)
(slave is transmitting data to a master)
(slave is receiving data from the master)
2
2
C bus specifies two signal connections:
C bus can operate with one or more master
I
2
C Mode Overview
shows the block diagram of the MSSPx
shows a typical connection between two
2
C mode.
2
C) is a multi-master
Preliminary
FIGURE 15-11:
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDAx line low to indicate to the
transmitter that the slave device has received the
transmitted data and is ready to receive more.
The transition of data bits is always performed while the
SCLx line is held low. Transitions that occur while the
SCLx line is held high are used to indicate Start and
Stop bits.
If the master intends to write to the slave, then it
repeatedly sends out a byte of data, with the slave
responding after each byte with an ACK bit. In this
example, the master device is in Master Transmit mode
and the slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this
example, the master device is in Master Receive mode
and the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDAx line
while the SCLx line is held high.
In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I
• Single message where a master writes data to a
• Single message where a master reads data from
• Combined message where a master initiates a
slave.
a slave.
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Master
2
C bus specifies three message protocols;
SCLK
SDIx
V
V
I
SLAVE CONNECTION
2
DD
DD
 2010 Microchip Technology Inc.
C™ MASTER/
SCLK
SDOx
Slave