MA160014 Microchip Technology, MA160014 Datasheet - Page 258

• Manufacturer Part Number: MA160014
• Description: MOD PLUG-IN 44PIN PIC18LF45K22
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of MA160014

• Accessory Type: Plug-In Module (PIM) - PIC18LF45K10
• Product: Microcontroller Modules
• Data Bus Width: 8 bit
• Core Processor: PIC18LF45K22
• Interface Type: I2C, SPI
• Operating Supply Voltage: 1.8 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM PIC18 Explorer, DM183032
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
REGISTER 15-3:
DS41412D-page 258
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GCEN
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
GCEN: General Call Enable bit (in I
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I
1 = Acknowledge was not received
0 = Acknowledge was received
ACKDT: Acknowledge Data bit (in I
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
ACKEN
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
0 = Acknowledge sequence idle
RCEN
1 = Enables Receive mode for I
0 = Receive idle
PEN
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
Automatically cleared by hardware.
R-0
(1)
(1)
SSPxCON2: SSPx CONTROL REGISTER 2
(1)
(1)
: Stop Condition Enable bit (in I
: Start Condition Enabled bit (in I
(1)
: Repeated Start Condition Enabled bit (in I
: Receive Enable bit (in I
: Acknowledge Sequence Enable bit (in I
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
ACKDT
R/W-0
ACKEN
R/S/HC-0
2
C
2
Preliminary
C Master mode only)
2
2
C mode only)
C Slave mode only)
2
(1)
C Master mode only)
2
2
C mode only)
C Master mode only)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware
R/S/HC-0
RCEN
2
C module is not in the Idle mode, this bit may not be
2
(1)
2
C Master mode only)
C Master mode only)
R/S/HC-0
PEN
(1)
 2010 Microchip Technology Inc.
S = User set
R/S/HC-0
RSEN
(1)
R/W/HC-0
SEN
(1)
bit 0