MA160014 Microchip Technology, MA160014 Datasheet - Page 373

MOD PLUG-IN 44PIN PIC18LF45K22

MA160014

Manufacturer Part Number
MA160014
Description
MOD PLUG-IN 44PIN PIC18LF45K22
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of MA160014

Accessory Type
Plug-In Module (PIM) - PIC18LF45K10
Product
Microcontroller Modules
Data Bus Width
8 bit
Core Processor
PIC18LF45K22
Interface Type
I2C, SPI
Operating Supply Voltage
1.8 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PICDEM PIC18 Explorer, DM183032
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA160014
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
MA160014
Manufacturer:
MICROCHIP
Quantity:
12 000
25.1.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
W
W
Q1
STANDARD INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
=
=
10h
25h
literal ‘k’
ADD literal to W
ADDLW
0  k  255
(W) + k  W
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
1
1
ADDLW
Read
0000
Q2
15h
k
1111
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
Preliminary
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
ADD W to f
ADDWF
0  f  255
d  [0,1]
a  [0,1]
(W) + (f)  dest
N, OV, C, DC, Z
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
ADDWF
Read
0010
Q2
17h
0C2h
0D9h
0C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
DS41412D-page 373
ffff
for details.
destination
Write to
Q4
ffff

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