MA160014 Microchip Technology, MA160014 Datasheet - Page 388

MOD PLUG-IN 44PIN PIC18LF45K22

MA160014

Manufacturer Part Number
MA160014
Description
MOD PLUG-IN 44PIN PIC18LF45K22
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of MA160014

Accessory Type
Plug-In Module (PIM) - PIC18LF45K10
Product
Microcontroller Modules
Data Bus Width
8 bit
Core Processor
PIC18LF45K22
Interface Type
I2C, SPI
Operating Supply Voltage
1.8 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PICDEM PIC18 Explorer, DM183032
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA160014
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
MA160014
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC18(L)F2X/4XK22
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
DS41412D-page 388
Q Cycle Activity:
After Instruction
operation
Decode
PC =
Q1
No
Address (THERE)
Read literal
operation
Unconditional Branch
GOTO k
0  k  1048575
k  PC<20:1>
None
GOTO
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO
instruction.
2
2
GOTO THERE
‘k’<7:0>,
1110
1111
Q2
No
allows an unconditional branch
is always a two-cycle
k
1111
19
operation
operation
kkk
Q3
No
No
k
kkkk
7
kkk
Read literal
Write to PC
‘k’<19:8>,
operation
Q4
No
kkkk
kkkk
Preliminary
0
8
INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
C
DC
CNT
Z
C
DC
Q1
=
=
=
=
=
=
=
=
register ‘f’
Increment f
INCF
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
INCF
C, DC, N, OV, Z
Read
0010
Q2
FFh
0
?
?
00h
1
1
1
 2010 Microchip Technology Inc.
f {,d {,a}}
10da
CNT, 1, 0
Process
Data
Q3
ffff
for details.
destination
Write to
Q4
ffff

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